1. Technical Field
Example embodiments relate to a semiconductor device, and more particularly, to a cache memory capable of adjusting the burst length of write-back data in a write-back operation, and a system including the cache memory.
2. Description of Related Art
To embody a high performance product capable of efficiently using a main memory and performing faster memory access, use of a cache memory or a write buffer has gradually increased not only in a central processing unit (CPU) but also in various co-processors, for example, 3D graphics processors. The cache memory is a high-speed memory device which stores a portion of the data stored in main memory that is frequently accessed by the CPU. The cache memory may read and write data at high speed, that is, tens to hundreds of times faster than a hard disk drive (HDD) reads and writes data.
That is, the cache memory stores data having a high frequency of use in a high-speed memory device, of the data stored in the main memory, and instantly outputs corresponding data according to a request by the CPU. Accordingly, desired data may be accessed at higher speed, compared to a case in which all data is stored in a low-speed memory device, for example, the HDD. Thus, when the data already read by the CPU is repeatedly accessed, the cache memory may access the data very quickly, in contrast with the case of a first access of the data from the main memory. As a result, the efficiency of a system using the cache memory is improved.
The cache memory includes a write-through cache and a write-back cache. The write-through cache, during a write operation, updates data stored in a block of the write-through cache with written data (hereinafter, referred to as the “write data”) and simultaneously updates data stored in the main memory with the write data. The write-back cache updates only data stored in a block of the write-back cache with the write data, during the write operation. When a cache miss is generated during a subsequent read operation, the write-back cache updates the data stored in the main memory with the write data, only when a block that needs to be emptied to store data corresponding to a data request signal output by the CPU in the block of the write-back cache includes the write data. The write-back cache is widely used to reduce the frequency of data accesses to the main memory.
In general, since the number of blocks to be stored in a cache memory is limited, when all blocks in the cache memory include the write data, that is, in a case of dirty or update, at least one block needs to be emptied for the next data access. Also, since the cache memory accesses data of the main memory in units of blocks and a processor accesses data of the cache memory in units of words, only a portion of the data in the block is usually changed.
A conventional computer system, for example, a microprocessor, does not need a cache memory having a large sized block. Thus, since the block size of the cache memory is small, any waste of bandwidth is not significant even when data that is not updated is transmitted to the main memory via a system bus. The bandwidth signifies a data transmission quantity, that is, the amount of data that can be transmitted by the cache memory to the main memory at one time.
However, as more diverse applications for cache memory are developed and the required amount of data transmission in systems increases, a cache memory having a block of a larger size, for example, 64 bytes or more, is required in a computer system, in particular, multimedia hardware. For processing such a large amount of data, the bandwidth of a system bus is increased to 64 bits or 128 bits.
Accordingly, in a conventional cache memory, since not only the write data in a block but also data that is not written is all transmitted to the main memory via the system bus, a large amount of the bandwidth is wasted. Thus, there is a demand for a cache memory that may decrease the bandwidth by adjusting the burst length of write-back data during the write-back operation.